The Electrostatic Discharge (ESD) sensitivities of on-chip resistors can be a problem for both electronic manufactures and electronic component users. As others components, passive devices are known to be susceptible to ESD events. The context of this invention is to improve the reliability of the resistors during an ESD event. An ESD stress caused by such an event means that high current and high voltage levels are applied to the device. The device has to be able to dissipate this energy without failure. Several articles have already put in some enhancements for meander resistor designs (see e.g. T. T. Lai, Electrostatic Discharge Sensitivity of Thin Film Hybrid Passive Components, 0569-550389/0229 IEEE, pp 229-239). These enhancements are based on a study on current densities within inner corners of a meander resistor (i.e. rounded corners provide a more uniform current density in such an area). But, it appears that is not sufficient and the present invention will describe a new resistor layout that creates a breakthrough in term of ESD sensitivity.
JP02197162 A discloses a resistor, in order to enable a diffusion resistor to vary in resistance by stages in accordance with the increase of an applied voltage by a method wherein a diffusion layer is formed in such a constitution that two different spaces are combined to be provided in the diffusion layer. A P-type diffusion layer is formed in meanders on an N-type Si substrate, which is covered with a SiO2, and electrodes are provided, which are covered with a SiO2. When a p-n junction is reversely biased, a depletion layer is made to expand toward the substrate side at a low voltage. When an A1 film is provided onto the P+ layer to serve as an optical shielding layer and connected to the electrode of a low voltage, a depletion can be made to spread at a low voltage. When a reverse bias exceeds a specified value, depletion layers are linked together in the substrate and a current flows direct without meandering, so that the diffusion layer decreases in resistance. If the depletion layers are not linked together, the layer is high in resistance. In the diffusion layer, when the combination of two different spaces in the layer is changed, the layer of optional resistance change characteristic can be realized.
Thus a meander resistor is disclosed being improved against high voltage stress applied on it. It seems diffusion zones are used to sink the current not through the meander path, but directly between two active diffusions nearby. As such a parasitic device of the resistor (in this case a PNP bipolar transistor) is triggered. Indeed this might be a way to increase its robustness with respect to ESD or EOS (electrical over stress). However, it only refers to a so-called diffusion resistor, which is built inside a substrate. Furthermore it does not relate to a specific layout of the resistor. In addition, it does not relate to meander resistors made on top of several substrates, such as silicon, laminate and LTCC. The validation part showed the case of polysilicon resistors, but it is known that all metallic resistors will exhibit the same improvement.
JP03054854 discloses a semiconductor device in order to prevent current concentration of a bending part while improving breakdown strength of a resistance film at the time of impressing electrostatic energy by making a bending part of the resistance film constituting an input protective circuit of a MOS element higher in impurity concentration than the other part and making the resistance low. An impurity is additionally doped to a bending part of a polycrystalline Si resistance film for an input protective circuit of an element on a semiconductor substrate having laminated MOS elements. Accordingly, the bending part gets higher impurity concentration than the other part for having low resistance. Thereby, current concentration inside the bending part at the time of impressing electrostatic energy is prevented, and as a result puncture voltage of polycrystalline Si resistance consisting of a bent resistance film is improved so that electrostatic breakdown strength of the input protective circuit of a laminated MOS element is improved.
This patent focuses on the doping profile of the bended resistor to improve its ESD sensitivity. This is different from a layout design improvement, without virtually any modification of the process step.
Thus, the above resistors, still suffer from reliability problems which need to be improved in terms of ESD stresses. Actually, a goal of the present invention is to reduce the risk of failure of a non diffused (back-end) resistor due to an ESD/EOS stress by a simple modification, and without virtually any modification of the process steps involved in manufacturing such a resistor.
Thus, in view of the above problems, there still is a need for improved meander resistors.
The present invention aims to overcome one or more of the above-mentioned problems and/or disadvantages, without jeopardizing other characteristics, by providing an improved meander resistor.